nand2mario / snestang
Super Nintendo Entertainment System for Tang Primer 25K FPGA
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Super Nintendo Entertainment System for Tang Primer 25K FPGA
Common SystemVerilog components
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Pipelines the AXI path with FIFOs
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
OpenTitan: Open source silicon root of trust
Simple single-port AXI memory interface
FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
AXI Adapter(s) for RISC-V Atomic Operations